GB/T 46280.1-2025 Specification for chiplet interconnection interface—Part 1: General principles English, Anglais, Englisch, Inglés, えいご
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ICS31.200
CCSL55
National Standard of the People's Republic of China
GB/T46280.1-2025
Specification for chiplet interconnection interface-Part 1: General principles
Released on August 19, 2025 Implementation on March 1, 2026
State Administration for Market Regulation, National Standardization Administration
Contents
Preface
Introduction
1 Scope
2 Normative references
3 Terms and Definitions
4 Abbreviations
5 Layered Architecture
5.1 Overview
5.2 Protocol Layer
5.3 Data Link Layer
5.4 Physical Layer
5.5 Bandwidth Application Mode
6 Internet Scenarios
7 Package Type
7.1 2D Packaging
7.2 2.5D Package
Specification for chiplet interconnection interface-Part 1: General principles
1 Scope
This document defines the terms, definitions, and abbreviations of the chiplet interconnect interface, specifies the layered architecture of the chiplet interconnect interface and the basic functions of each layer, and establishes interconnection scenarios and packaging types.
This document applies to the design, manufacture and application of chiplet interconnect interfaces.
2 Normative references
The contents of the following documents constitute essential provisions of this document through normative references. For dated references, only the version corresponding to that date applies to this document. For undated references, the latest version (including all amendments) applies to this document.
GB/T9178 Integrated Circuit Terminology
GB/T14113 Semiconductor Integrated Circuit Packaging Terminology
3 Terms and Definitions
The terms and definitions defined in GB/T 9178 and GB/T 14113 and the following apply to this document.
3.1
Bare chip die is an
unpackaged independent integrated circuit chip obtained by dicing the wafer that has completed the integrated circuit preparation.
3.2
Chiplet is a bare chip or
chip that has some of the system's functions and is connected to other parts of the system through a high-bandwidth interconnect interface or analog interface within the package.
Integrated bare chip. Note:
Usually has a certain degree of reusability, with multiple chips integrated into an integrated circuit system through high-bandwidth interconnection.
3.3
2D package 2D package is a
packaging form of traditional substrate-type flip chip (3.16).
3.4
2.5D package 2.5D package is a packaging
form that can integrate multiple chips and components on the same substrate.
Note: Common packaging types include fan-out (3.17) organic interposer packaging, inorganic interposer (3.18) packaging, and embedded bridge packaging.
form.
3.5
Interconnect The physical
connection lines between chiplets.
3.6
Intercommunication is based on the physical
connection between the core particles, and uses the communication protocol to coordinate and schedule the connection lines for information exchange between the two ends.
3.7
Packet: A data unit
generated by a protocol adapter unit.
3.8
Data block flowcontrolunit The basic data
unit transmitted by the data link layer.
3.9
Transmitterlane: A collection of physical layer data
input/output ports that share the same differential clock in the sending direction.
3.10
Receive data path receiverlane The set of
physical layer data input/output ports that share the same differential clock in the receive direction.
3.11
Sideband channel is a channel
that cooperates with the data channel to transmit control signals.
3.12
A macro is a collection of
multiple channels that share the same set of sideband channels.
3.13
A link is a data
transmission unit that can carry out orderly and reliable data transmission and realize shared unified data management.
3.14
Bumps are physical
structures in packages used to connect the chip to the interposer or substrate.
Note: Usually composed of solder and metal.
3.15
Bump pitch is the distance between the
center point of a bump and the center point of the adjacent bump.
3.16
Flip chip is a packaging technology
that electroplates bumps on the chip and then flips the chip over to connect the bumps to the substrate.
3.17
Fanout is a packaging
technology that redistributes chip pins based on rewiring layer technology, and the array area bounded by the new pins is larger than the original chip area.
3.18
Interposer: A physical structure
in a package that carries the connections between the chip and the substrate.
4 Abbreviations
The following abbreviations apply to this document.
ACE: AXI Coherency Extensions
AXI: Advanced Extensible Interface
CHI: Coherent Hub Interface
CPIF: ChipletPHYInterface
CRC: Cyclic Redundancy Check
ECC: Error Correction Code
Flit: data block (Flow control unit)
HAI: High bandwidth memory access interface (HighbandwidthmemoryAccessInterface)
IO: Input/Output
PAIF: Protocol Adapter Interface
PHY: Physical Layer
RX: Receiver
SoC: System on Chip
TX: Transmitter
5 Layered Architecture
5.1 Overview
The layered architecture of chiplet interconnection is shown in Figure 1.
Figure 1: Layered architecture of chiplet interconnection
In the sending direction, application data is received through the protocol layer, converted to Flit format through PAIF to the data link layer, and then divided into
The data is sent to the physical layer and transmitted to another chip through the encapsulated connection. In the receiving direction, the data received by the physical layer is transmitted to the data link layer through the CPIF for processing, and then transmitted to the protocol layer through the PAIF, and then sent to the upper layer application.
5.2 Protocol Layer
The protocol layer includes the bus adapter unit and the HAI/custom processing unit. The bus adapter unit should implement the following functions:
- Define a specific format to package data from different bus protocols; - Arbitrate multi-
protocol bus transmissions; - Data caching. For typical applications, the following service protocols are supported: - SoC bus protocol:
Defines common SoC bus carrying rules, supports AXI4.0/3.0 bus protocols, and is scalable to
